Dynamic Random Access memories (DRAM) contain an array of DRAM memory cells and supporting circuitry Embedded DRAM (eDRAM) is usually integrated on the same die or in the same package as the main processor (or application specific integrated circuit), as opposed to external DRAM modules. Unlike Static Random Access Memory (SRAM), DRAM memory cells must be refreshed (i e, they must be read and re-written periodically in order to retain data). The refresh operation is required because data is stored in the form of a charge within a capacitor and that charge slowly leaks from the capacitor.
Idle cycle refresh (ICR) is a common refresh control method for eDRAM. ICR requires a system using eDRAM to reserve clock cycles during which the eDRAM is refreshed. During the reserved refresh clock cycles, the eDRAM cannot be accessed for a read or a write operation. Thus, the data transfer rate between the system and eDRAM is reduced by the percentage of cycles that are reserved for ICR (typically as much as a 6% reduction). Based on a typical ICR implementation, the eDRAM reserves more idle cycles than it actually needs and uses for refresh cycles. Generally, the frequency of cycles reserved for idle cycles is often specified based upon a worst case scenario, such as a fast silicon process and/or an operating environment that has the highest memory cell leakage. It is thus desirable to improve the data transfer rate between eDRAM and the user system by only reserving idle cycles that the eDRAM actually needs and will use for refresh cycles.